PCI (Peripheral Component Interconnect)

PCI, and PCI Express after it with the same software model, connects most devices in a PC and in many ARM machines. Software addresses a device by where it sits: a segment (a group of buses), a bus number, a device number on that bus (0 to 31) and a function number (0 to 7). The function is the unit a driver binds, because one physical device can hold up to eight independent functions, such as a graphics card and its audio controller.

Each function has a configuration space, 256 bytes in classic PCI and 4 KiB in PCI Express, which opens with a standard header. Its vendor id and device id name the exact chip, and three class bytes (class, subclass and programming interface) say what kind of device it is. Optional features such as MSI-X (interrupt delivery) are announced in a capability list, a chain of entries that each hold an id and the offset of the next. The header also holds the command register, whose bits decide whether the function answers memory accesses, answers I/O port accesses, and may start DMA on its own (bus mastering).

A function's registers have no fixed address. Each of its six base address registers (BARs) asks for a memory window or an I/O port range of a fixed size, and a 64-bit memory BAR takes two of the six slots. Something must give every BAR an address, and the firmware does so during boot (firmware handoff), which leaves a device plugged in later without one (hot-plug).

Configuration space is reached in one of two ways. The legacy x86 mechanism writes a function's address to port 0xCF8, moves the data through port 0xCFC, and reaches only the first 256 bytes. ECAM (enhanced configuration access mechanism) maps every function's full 4 KiB into a memory window, whose base ACPI or the device tree gives.

The trap is a match on the class alone. A class says what a device does, not how it is programmed: every network controller is class 0x02, whoever made it, so a driver matching that class is offered chips whose registers it has never seen. The class bytes pin down a programming model only where a standard defines one, such as xHCI, EHCI, OHCI, AHCI, NVMe or HD Audio.

In the driver kit, PciMatch tests the header fields of a PciIdentity, whose node path is pci:<segment>:<bus>:<device>.<function> (PCI identity and match), and PciAccess offers FindCapability and the command register bits as EnableMemorySpace, EnableIoSpace and EnableBusMastering (The PCI access object). Node.Resources holds the BARs as the firmware assigned them, or as the kit placed them behind a hot-plug slot, None marking an unassigned slot or the upper half of a 64-bit BAR (BAR resources). The x64 host is pci-host-legacy, where a configuration access past offset 255 throws, and the ARM64 host is pci-host-ecam-generic (Platform nodes).