DMA (direct memory access)

With programmed I/O the CPU copies every word through a device register itself, which would keep a core busy for a fast network card or disk. With direct memory access the device reads and writes main memory on its own: the driver gives it the physical address and length of a buffer, usually through a descriptor ring, the device moves the data while the CPU does other work, and it reports completion, often with an interrupt.

A device that starts memory transactions on its own is a bus master. On PCI a function may do so only while the Bus Master Enable bit of its Command register is set, which lets the operating system stop it. Some devices drive only 32 address bits and reach only the first 4 GiB of physical memory.

The CPU caches memory, and a device working behind the caches could read stale data or leave stale lines. On a coherent platform, which x64 PCs are, the hardware keeps device accesses consistent with the caches; on a non-coherent one the driver cleans or invalidates cache lines around every transfer. Coherence orders nothing, though, so a driver still needs barriers between writing data and telling the device it is there.

The trap is that DMA bypasses everything the kernel uses to protect memory. A device keeps writing to the address it was given until it is stopped, so a buffer freed while a transfer is in flight is overwritten inside whatever reuses it. A garbage collector adds a way to free one by surprise: it reclaims an object once no reference remains, and an address in a descriptor is not a reference it can see.

In the driver kit, a DmaBuffer from binding.AllocateDma lives until teardown frees it after OnDetach, so a driver hands a device only such buffers, never a managed array. TryAllocateDma with DmaConstraints.Addressable32Bit returns false for a buffer that would end above 4 GiB: the kit has no pool of low memory, so it allocates as usual and gives such a buffer back. The kit treats DMA as coherent on x64 and ARM64. It turns bus mastering off on a PCI function before the first probe, and again after each probe that does not bind, before that probe's buffers are freed, so every probe starts from a function that cannot write to memory and a declined probe's device stops before its buffers go back; a driver turns it back on with PciAccess.EnableBusMastering(true). See DMA memory and The PCI access object.