LAI (Lightweight ACPI Implementation) via C interop.
Interrupt Handling
✅
✅
x64: APIC (Local + I/O). ARM64: GIC.
Memory Management
✅
✅
Driver support
✅
✅
PCI and MMIO over the driver kit; the platform bus seeded from ACPI, the device tree (ARM64) or the machine's table; PCI Express hot-plug on root ports
Garbage Collection
✅
✅
Mark-and-sweep GC
Filesystem
✅
✅
FAT12/16/32 on a Unix-style VFS (mount, superblocks, inodes) with formatting; MBR/GPT/EBR partitioning. Exposed through System.IO.File/FileStream.
The firmware framebuffer via Limine, plus the virtio-gpu, VMware SVGA II, AMD DCN 3.1.5 and Intel integrated graphics display drivers over the driver kit (SVGA3D on the VMware one).
Network interface
✅
✅
Timer / Clock
✅
✅
Keyboard Input
✅
✅
PS/2 (x64), virtio and USB keyboards, all as driver kit drivers
Mouse Input
✅
✅
PS/2 (x64), virtio and USB mice, all as driver kit drivers
Audio interface
🟡
✅
Intel HD Audio: WAV playback, generated streams and Console.Beep. Playback only, one stream per output.
Additional Gen3 Features
Beyond Gen2 parity, Gen3 brings new capabilities:
Feature
Status
Notes
NativeAOT Runtime
🟡 Partial
Full NativeAOT compilation with runtime, no IL2CPU.
xHCI host controller with hubs and hot-plug (x64 + ARM64) as driver kit drivers, with the HID boot keyboard, HID boot mouse and mass storage (Bulk-Only Transport) class drivers. No EHCI yet.
Future Releases
Features planned after first release:
Feature
Status
Notes
SMP (Symmetric Multiprocessing)
❌ Not Started
Multi-core AP boot, per-CPU scheduling, load balancer.
Replace current mark-and-sweep with generational collector (Gen0/Gen1/Gen2) for better performance.
Code execution
❌ Not Started
Userland WASM VM
The GIC, the ITS and the clocks from the device tree
❌ Not Started
Today the ARM64 interrupt controller comes from ACPI or the virt defaults, so an acpi=off boot has no MSI; the platform bus already reads the tree. x64 never has one.
PCI hot-plug beyond native PCI Express slots
❌ Not Started
ACPI (GPE) hot-plug, which QEMU uses on q35's root ports without the ICH9-LPC global and on conventional PCI bridges; downstream switch ports are matched but untested.